The Dawn of AI Silicon: Why Chips Became the New Currency of Power

The Dawn of AI Silicon: Why Chips Became the New Currency of Power

On a Tuesday in November 2022, OpenAI released ChatGPT to the public. Within five days, the service had attracted one million users; within two months, it had become the fastest-growing consumer application in history. Behind that conversational interface, however, sat a far less visible revolution: thousands of specialized processors, designed for nothing but the rapid multiplication of enormous matrices, were burning through electricity in data centers from Arizona to Finland. The product was software; the substance was silicon. The launch was a public event; the substrate was a geopolitical one. Understanding this inversion—where chips, not algorithms, became the binding constraint on artificial intelligence—is the purpose of this opening chapter.

The question this book asks is deceptively simple. For half a century, the computer industry treated processors as interchangeable commodities: faster, cheaper, and more numerous with every generation, but fundamentally similar in what they did. Software was where the value lived. Firms competed on operating systems, applications, and user experience. Hardware was a means to an end. Yet between roughly 2012 and 2024, the locus of value quietly migrated from the instruction set to the integrated circuit. A new class of device—variously called an AI accelerator, a neural processing unit, or simply an AI chip—emerged to perform a single class of computation so efficiently that owning them became a strategic asset on par with oil reserves or telecommunications spectrum. Three companies, in particular, came to define the frontier: NVIDIA, whose H100 became the default currency of model training; Google, whose Tensor Processing Unit (TPU) demonstrated that hyperscalers could design their own silicon; and Huawei, whose Ascend family showed that the geography of advanced AI hardware was no longer the exclusive preserve of the United States and its allies. The story of how this happened, and what it means, is the story of this book.

This chapter lays the groundwork. It begins with the historical transition from general-purpose CPUs to domain-specific AI silicon, anchored by the public launches of the NVIDIA H100, Google TPU v5p, and Huawei Ascend 910C. It then examines how AI workloads—dominated by matrix multiplication and tensor operations—stress traditional processor architectures in ways that make the same silicon that excels at spreadsheets unable to train a language model. The discussion then widens to the economic surge: the trillions of dollars now flowing into data centers, the reordering of corporate valuations, and the emergence of chip sovereignty as a category of national policy. Three short vignettes follow—training GPT-4, real-time inference of Google's Gemini, and the deployment of large-scale recommendation systems in Chinese e-commerce—to make these abstractions concrete. The chapter closes by previewing the comparative framework—architecture, memory, software, ecosystem, and geopolitics—that will structure the next fourteen chapters.

The Historical Transition: From General-Purpose CPUs to Domain-Specific AI Silicon

The first transistors were generalists. Whether the machine was balancing a checkbook, simulating a nuclear reaction, or printing a payroll, the underlying hardware performed essentially the same set of operations: fetch an instruction, decode it, execute it, and store the result. This von Neumann model, named after the mathematician John von Neumann, dominated computing for seventy years. It survived the move from vacuum tubes to discrete transistors, from transistors to integrated circuits, and from integrated circuits to multi-core processors. The reason for its durability is straightforward: a general-purpose machine can run any program, which means a single design can serve an enormous market. Economies of scale reward universality.

For most of that history, software innovation outpaced hardware specialization. Operating systems evolved from batch monitors to time-sharing systems to graphical environments; programming languages moved from machine code to high-level abstractions; applications expanded from spreadsheets to web browsers to mobile apps. The hardware, meanwhile, simply got faster. The famous observation by Intel co-founder Gordon Moore—that the number of transistors on a chip would double roughly every two years—held for half a century, delivering a steady cadence of performance improvements that software developers could rely on. When programmers needed more speed, they could wait. When they could not wait, they wrote more efficient code. The hardware was rarely the bottleneck.

Three things changed. The first was the breakdown of Dennard scaling around 2006: as transistors shrank, the voltage required to operate them stopped falling in step, which meant that clock speeds could no longer be increased without generating unsustainable heat. The industry responded by placing multiple processor cores on a single chip, but parallel programming proved far harder than engineers had hoped. The second was the rise of deep learning, beginning with the 2012 ImageNet competition in which a neural network trained on graphics processing units (GPUs) demolished the field. Researchers had discovered, almost by accident, that the highly parallel architecture originally designed for rendering video games was exceptionally well suited to the dense linear algebra at the heart of neural networks. The third was the staggering growth in the size of those networks: GPT-2 had 1.5 billion parameters; GPT-3 had 175 billion; GPT-4 was rumored to be more than a trillion. When models crossed a certain threshold of scale, the cost of training them on general-purpose hardware became economically untenable. A new class of chip was needed.

The launch of the NVIDIA H100 in March 2022 marked a symbolic moment in this transition. Built on TSMC's N4 process, the H100 packed 80 billion transistors into a single die, an order of magnitude more than a typical server CPU. Its most important feature, however, was not raw transistor count but a specialized engine called the Transformer Engine, designed specifically to accelerate the matrix multiplications that dominate transformer-based language models. The chip could perform certain operations at four times the speed of its predecessor, the A100, while consuming less energy per operation. Customers did not merely want the H100; they could not get enough of it. By 2023, lead times stretched to six months, and the chip traded on secondary markets at multiples of its list price. In the words of one industry analyst, the H100 had become "the most valuable square of silicon ever sold."

Google's TPU v5p, announced in December 2023, represented a different philosophy. Where NVIDIA sold accelerators to anyone with a credit card, Google designed the TPU primarily for its own data centers, where it powered Search, YouTube, and increasingly the training and inference of large language models including Gemini. The TPU family began as a research project in 2013, when Google engineers concluded that neither CPUs nor GPUs would allow the company to scale voice search to a billion users at acceptable cost. Each generation added capabilities: systolic arrays for matrix multiplication in v1 and v2; high-bandwidth memory and larger chips in v3; optical packaging in v4. The v5p pushed performance further still, with 8,960 chips per pod and a custom interconnect capable of moving terabytes of data per second between them. Crucially, the TPU was not a commercial product in the traditional sense: it was infrastructure, designed to make Google's services cheaper and faster. The fact that Google began renting access to TPU pods through Google Cloud reflected a strategic decision to monetize excess capacity, not a pivot to a chip business.

Huawei's Ascend 910C, expected in 2024 and 2025, completed the