计算范式的演变：从CPU到AI芯片

计算作为人类文明的核心驱动力，其发展轨迹深刻塑造了从工业革命到信息时代的每一次社会变革。在过去半个多世纪里，以中央处理器（Central Processing Unit, CPU）为代表的通用计算架构一直是推动计算能力提升的主要引擎。然而，随着人工智能（Artificial Intelligence, AI）特别是深度学习技术的迅猛发展，传统通用处理器在应对现代机器学习 workloads 时日益显现出架构层面的局限性。这一矛盾催生了AI芯片这一新兴技术领域的崛起，也标志着计算范式从“通用为王”向“领域定制”的深刻转型。

Computing, as a core driving force of human civilization, has profoundly shaped every social transformation from the Industrial Revolution to the Information Age. Over the past half-century, general-purpose computing architectures represented by the Central Processing Unit (CPU) have been the primary engine driving computational capability improvements. However, with the rapid advancement of artificial intelligence (AI), particularly deep learning technologies, traditional general-purpose processors increasingly reveal architectural limitations when handling modern machine learning workloads. This contradiction has catalyzed the rise of AI chips as an emerging technology domain, marking a profound transformation in computing paradigms from "universality reigns supreme" toward "domain-specific customization."

本章将系统梳理计算架构从CPU主导时代到AI芯片崛起的演进历程，深入分析摩尔定律放缓背景下领域特定架构（Domain-Specific Architecture, DSA）兴起的深层原因，并通过剖析冯·诺依曼架构的基本原理及其在深度学习场景下的性能瓶颈，阐明为何传统通用处理器难以有效满足现代AI workloads 的算力需求。本章还将引入计算机体系结构的基本评估维度——性能（Performance）、功耗（Power）、面积（Area）和成本（Cost），统称为PPAK框架，为后续各章节的架构分析提供统一的评判标准和方法论基础。

This chapter systematically traces the evolution of computing architectures from the CPU-dominated era to the rise of AI chips, deeply analyzing the underlying reasons for the emergence of Domain-Specific Architectures (DSA) in the context of slowing Moore's Law. By examining the fundamental principles of the von Neumann architecture and its performance bottlenecks in deep learning scenarios, this chapter clarifies why traditional general-purpose processors cannot effectively meet the computational demands of modern AI workloads. Additionally, this chapter introduces the fundamental evaluation dimensions of computer architecture—Performance, Power, Area, and Cost, collectively referred to as the PPAK framework, providing a unified evaluation standard and methodological foundation for architectural analysis in subsequent chapters.

通用计算时代的辉煌与局限

The Glory and Limitations of the General-Purpose Computing Era

要理解AI芯片崛起的必然性，首先需要回顾通用处理器时代的辉煌成就。1965年，英特尔（Intel）联合创始人戈登·摩尔（Gordon Moore）在《电子学》杂志（Electronics Magazine）上发表了一篇具有里程碑意义的论文，首次提出了后来被称为“摩尔定律”的预测：集成电路上可容纳的晶体管数量大约每两年翻一番，同时价格保持不变或降低一半。这一观察后来成为半导体行业长达半个世纪的发展蓝图和技术路线图的核心指导原则。

To understand the inevitability of AI chip emergence, we must first review the glorious achievements of the general-purpose processor era. In 1965, Gordon Moore, co-founder of Intel, published a landmark paper in Electronics Magazine, proposing for the first time what would later be known as "Moore's Law"—the prediction that the number of transistors on an integrated circuit would approximately double every two years, while the cost remains the same or decreases by half. This observation became the core guiding principle for the semiconductor industry's development blueprint and technology roadmap for half a century.

摩尔定律的持续有效性为计算产业带来了指数级的性能提升。从1971年英特尔推出首款商用微处理器4004（包含2300个晶体管）到2020年代先进制程芯片（包含数百亿个晶体管），五十年间晶体管密度提升了超过十亿倍。这种近乎不可思议的增长速度使得通用处理器能够持续满足日益复杂的计算需求，从早期的科学计算、文本处理到后来的图形渲染、网络服务，CPU始终扮演着核心计算引擎的角色。

The continuous validity of Moore's Law brought exponential performance improvements to the computing industry. From Intel's launch of the first commercial microprocessor, the 4004 (containing 2,300 transistors) in 1971, to advanced process chips in the 2020s (containing hundreds of billions of transistors), transistor density increased by over a billion times in fifty years. This almost incredible growth rate enabled general-purpose processors to continuously meet increasingly complex computational demands, from early scientific computing and text processing to later graphics rendering and network services, with the CPU always playing the role of the core computing engine.

通用处理器设计的核心哲学建立在“单一处理器解决所有问题”的理念之上。这种设计范式的优势在于其无与伦比的灵活性——通过软件编程，同一款处理器可以执行从航空航天飞行控制到家庭财务管理等各种截然不同的任务。处理器的指令集架构（Instruction Set Architecture, ISA）提供了硬件与软件之间的抽象接口，使得程序员能够以相对统一的方式利用底层硬件资源，而无需关心具体的电路实现细节。

The core philosophy of general-purpose processor design is built on the concept of "a single processor solves all problems." The advantage of this design paradigm lies in its unparalleled flexibility—a single processor can execute vastly different tasks ranging from aerospace flight control to household financial management through software programming. The processor's Instruction Set Architecture (ISA) provides an abstract interface between hardware and software, enabling programmers to utilize underlying hardware resources in a relatively unified manner without concerning themselves with specific circuit implementation details.

然而，这种通用性是以效率为代价换取的。为了保持对各类应用的可编程性支持，通用处理器在硬件实现上必须做出诸多妥协。超标量（Superscalar）流水线、乱序执行（Out-of-Order Execution）、分支预测（Branch Prediction）、缓存层次结构（Cache Hierarchy）等复杂微架构技术的引入，固然显著提升了处理器的性能表现，但同时也带来了可观的硬件开销——相当比例的晶体管被用于控制逻辑和缓存系统，而非直接执行计算任务。此外，通用处理器需要支持复杂的指令集和多样化的数据类型，这些设计约束进一步限制了其在特定领域所能达到的效率极限。

However, this generality comes at the cost of efficiency. To maintain programmable support for various applications, general-purpose processors must make numerous compromises in hardware implementation. While complex microarchitecture techniques such as Superscalar pipelining, Out-of-Order Execution, Branch Prediction, and Cache Hierarchy significantly improve processor performance, they also bring considerable hardware overhead—a substantial proportion of transistors are used for control logic and cache systems rather than directly executing computational tasks. Furthermore, general-purpose processors need to support complex instruction sets and diverse data types, and these design constraints further limit the efficiency limits they can achieve in specific domains.

深度学习计算特征与通用架构的适配鸿沟

The Adaptation Gap Between Deep Learning Computing Characteristics and General-Purpose Architectures

深度学习的工作负载特征与传统计算任务存在本质差异，这构成了通用处理器在AI时代面临挑战的根本原因。深度神经网络（Deep Neural Networks, DNNs）的计算核心主要包含两类基本操作：矩阵-向量乘法（Matrix-Vector Multiplication）和矩阵-矩阵乘法（Matrix-Matrix Multiplication），以及激活函数（如ReLU、Sigmoid、Tanh等）的非线性变换。这些操作具有高度规则的计算模式、巨大的数据吞吐量需求以及相对简单的控制流要求。

The computational characteristics of deep learning workloads differ fundamentally from traditional computing tasks, which constitutes the root cause of challenges facing general-purpose processors in the AI era. The computational core of Deep Neural Networks (DNNs) primarily includes two basic operations: Matrix-Vector Multiplication and Matrix-Matrix Multiplication, along with nonlinear transformations of activation functions (such as ReLU, Sigmoid, Tanh, etc.). These operations have highly regular computational patterns, enormous data throughput requirements, and relatively simple control flow demands.

以经典的卷积神经网络（Convolutional Neural Network, CNN）为例，一个用于图像分类的现代CNN模型可能包含数千万到数亿个参数，需要执行数十亿次浮点运算（Floating Point Operations, FLOPs）来完成单张图像的推理。在训练阶段，由于反向传播算法（Backpropagation）需要反复遍历整个网络，这些计算量还要乘以训练数据集的规模和迭代次数。根据OpenAI的研究报告，从2012年到2018年，训练尖端AI模型所需的计算资源增长了超过30万倍，年均增长率约为10-11倍，远超摩尔定律所能提供的性能提升。

Take a classic Convolutional Neural Network (CNN) as an example: a modern CNN model for image classification may contain tens of millions to hundreds of millions of parameters, requiring billions of Floating Point Operations (FLOPs) to complete inference on a single image. In the training phase, due to the backpropagation algorithm requiring repeated traversal of the entire network, these computational requirements are multiplied by the training dataset size and the number of iterations. According to OpenAI research reports, from 2012 to 2018, computational resources required for training state-of-the-art AI models grew over 300,000 times, with an average annual growth rate of approximately 10-11 times, far exceeding the performance improvements Moore's Law can provide.

通用处理器在执行这些深度学习操作时面临多重效率瓶颈。首先，现代CPU采用的数